In recent years, active matrix liquid crystal displays have attracted attention. This kind of display device has several hundreds x several hundreds of pixel electrodes arranged in rows and columns. TFTs using a silicon thin film are used for these pixel electrodes. Electric charge to be held at each pixel is controlled by the corresponding TFT.
In principle, the liquid crystal display must transmit light and so the material of the substrate is required to transmit visible light. Examples of the material transmitting light include quartz and glass. Among them, quartz substrates are expensive and undesirable from an economical point of view. Accordingly, glass substrates have enjoyed wide acceptance. In this case, the problem is that how high-performance TFTs are fabricated on glass substrates.
The characteristics of TFTs can be improved most effectively by enhancing the crystallinity of the silicon thin film used. However, where a glass substrate is used, it is difficult to obtain a single-crystal silicon film or a silicon thin film having crystallinity comparable to that of a single-crystal silicon film. Silicon thin films generally produced are polycrystalline or microcrystalline assuming an imperfect crystal state.
Where a TFT is fabricated, using such a silicon thin film in a polycrystalline or microcrystalline state, the OFF current characteristics pose a great technical problem to be solved. Generally, where a TFT is manufactured, using a silicon thin film in a polycrystalline or microcrystalline state, the OFF current tends to be large. The OFF current is an electrical current flowing between the source and drain when the TFT is in its Off state.
It is now assumed that the source of a TFT arranged at a pixel is connected with a source line and that the drain is connected with a pixel electrode. When the TFT is driven into conduction, i.e., turned ON, a given amount of electric charge flows into the pixel electrode from the source line via the TFT. When the TFT is turned OFF, the charge is retained in the pixel electrode. If the OFF current of the TFT is considerably large, the electric charge gradually leaks from the pixel electrode. Of course, the given charge is not held in the pixel electrode for a given time. As a result, the required display is not provided.
It is considered that the problem of the OFF current is caused by the fact that carriers are moved through grain boundaries of crystals. For example, in the case of an N-channel TFT, when a positive potential is applied to the gate electrode, the channel is made N-type, and the TFT is turned ON. When a negative potential is applied to the gate electrode, the channel is rendered P-type, and the TFT is turned OFF.
When the TFT is turned OFF in this way, the source/drain are the N-type, and the channel becomes the P-type. Therefore, an NPN structure is formed between the source and drain. In principle, no current flows between the source and drain. However, this is an ideal case where the silicon thin film forming the active layer has a single-crystal structure.
In practice, carriers migrate through trap levels existing at grain boundaries. This migration results in an OFF current.
As mentioned previously, a crystalline silicon thin-film semiconductor formed on a glass substrate takes the form of polycrystals or microcrystals. That is, innumerable crystal grains exist in the film. Numerous trap levels exist at these grain boundaries.
The movement of the carriers through the trap levels is especially significant in regions to which a high electric field is applied. This phenomenon is especially noticeable at and near the channel-drain interface. Accordingly, it is known to form a field-relaxation region to suppress movement of the carriers through the trap levels. For this purpose, a lightly doped region or an offset region (also known as an offset gate region) is formed between the channel region and the drain region. These structures are known as the lightly doped drain (LDD) structure and the offset gate structure, respectively.
Where a crystalline silicon thin film is formed on a glass substrate and a TFT is manufactured in practice, using this silicon thin film, the above-described LDD structure or offset structure is useful and capable of suppressing the OFF current to some extent. However, the present situation is that it is difficult to obtain satisfactorily low OFF currents.
Generally, an active layer is formed by the following sequence. Resist is photolithographically patterned into desired form. Using this resist pattern as a mask, a dry etching process is carried out, using a plasma.
After earnestly investigating the aforementioned problem with the OFF characteristics of a TFT, the inventors of the present invention made the following findings.
When the dry etching process is performed to form the above-described active layer, the side surfaces of the active layer are plasma-damaged. As a result, trap levels are formed at a high density at the side surfaces of the active layer.
In a polycrystalline or microcrystalline silicon film in which trap levels exist at a high density, this phenomenon is remarkable. Consequently, trap levels are formed at a high density at the side surfaces of the active layer.
If numerous trap levels are created at the side surfaces of the active layer by the plasma damage, movement of carriers via the trap levels becomes remarkable. That is, the OFF current is increased. This problem is especially significant where the film contains innumerable grain boundaries as in the case of polycrystalline or microcrystalline silicon. This is because trap levels tend to be located and generated at grain boundaries.
The density of the trap levels formed at the side surfaces of the active layer is much higher than the density of the trap levels in the active layer or in the film. Therefore, even if the LDD structure or offset structure is adopted, the number of electric charges moved via the trap levels at the side surfaces of the active layer cannot be suppressed greatly. That is, it is impossible to lower the OFF current value greatly.
The LDD structure and the offset structure relax the electric field intensity in the region in which the electric field tends to be concentrated. This suppresses movement of carriers which are the cause of the Off current. In other words, the number of carriers moved is reduced. However, where the density of trap levels causing movement of carriers is quite high, even if the electric field strength is weakened, it is impossible to reduce the total number of carriers greatly.
The problem arises from trap levels concentrated at the side surfaces of the active layer. Accordingly, if the density of the trap levels at the side surfaces can be reduced, then the problem with the OFF current characteristics can be solved. As described previously, the main cause of the trap levels concentrated at the side surfaces of the active layer is plasma damage during formation of the active layer. Therefore, if this plasma damage can be reduced, then the problem with the OFF current of the TFT can be eased.
One example of the method for avoiding the plasma damage to side surfaces of the active layer may be to use a wet etching process when the active layer is formed. However, this presents various problems including:
(1) Any appropriate etchant capable of selectively etching only a silicon film with high controllability and high reproducibility is not available. PA1 (2) The temperature of the etchant used must be controlled strictly. Furthermore, delicate etching conditions are necessary.